Dear Dhaval, On Thu, Dec 7, 2017 at 10:31 PM, Dhaval Shah <dhaval.shah@xxxxxxxxxx> wrote: > Xilinx ZYNQMP logicoreIP Init driver is based on the new > LogiCoreIP design created. This driver provides the processing system > and programmable logic isolation. Set the frequency based on the clock > information get from the logicoreIP register set. > > It is put in drivers/misc as there is no subsystem for this logicoreIP. > > Signed-off-by: Dhaval Shah <dshah@xxxxxxxxxx> > --- > Changes since v2: > * Removed the "default n" from the Kconfig > * More help text added to explain more about the logicoreIP driver > * SPDX id is relocated at top of the file with // style comment > * Removed the export API and header file and make it a single driver > which provides logocoreIP init. > * Provide the information in commit message as well for the why driver > in drivers/misc. Thank you for the SPDX comments updates. Acked-by: Philippe Ombredanne <pombredanne@xxxxxxxx> -- Cordially Philippe Ombredanne -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
