On Wed, Nov 01, 2017 at 06:09:17PM -0700, Florian Fainelli wrote:
> On 11/01/2017 05:36 PM, David Daney wrote:
> > From: Carlos Munoz <cmunoz@xxxxxxxxxx>
> >
> > Add bindings for Common Ethernet Interface (BGX) block.
> >
> > Signed-off-by: Carlos Munoz <cmunoz@xxxxxxxxxx>
> > Signed-off-by: Steven J. Hill <Steven.Hill@xxxxxxxxxx>
> > Signed-off-by: David Daney <david.daney@xxxxxxxxxx>
> > ---
> [snip]
> > +Properties:
> > +
> > +- compatible: "cavium,octeon-7360-xcv": Compatibility with cn73xx SOCs.
> > +
> > +- reg: The index of the interface within the BGX block.
> > +
> > +- local-mac-address: Mac address for the interface.
> > +
> > +- phy-handle: phandle to the phy node connected to the interface.
> > +
> > +- cavium,rx-clk-delay-bypass: Set to <1> to bypass the rx clock delay setting.
> > + Needed by the Micrel PHY.
>
> Is not that implied by an appropriate "phy-mode" property already?
Hi Florian
Looking at the driver patch, phy-mode is not used at
all. of_phy_connect() passes a hard coded SGMII value!
David, you need to fix this.
Andrew
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