Gunter, This adds reset controller support to the ASPEED pwm/tach driver. The reset controller and clock driver is currently under review, so to test those patches must be merged in to fully test these changes[1]. To address your concerns from v1: This driver was not usable as-is upstream. I believe the developer(s) tested and deployed it in the OpenBMC kernel tree which has some hacks in mach-aspeed to release all of the resets. The other way they could have tested it is by booting an OpenBMC kernel, which releases the resets, and then testing the upstream kernel without performing a power cycle as the resets are not reasserted on reboot. I realise it is not ideal to be changing already merged bindings. I don't plan on it becoming a habit. There is no BIOS or other ROM that runs before Linux on a BMC to release the resets. We do have u-boot, but that does not modify the pwm reset. I haven't added a Kconfig dependency on the RESET_CONTROLLER as the driver can build without it, and when the ASPEED clk/reset driver is merged, the platform will always have that option selected. I've given this version a day of testing on hardware I have access to. [1] https://lwn.net/Articles/737697/ Joel Stanley (3): hwmon: (aspeed-pwm-tacho) Sort headers hwmon: (aspeed-pwm-tacho) Deassert reset in probe dt-bindings: hwmon: aspeed-pwm-tacho: Add reset node .../devicetree/bindings/hwmon/aspeed-pwm-tacho.txt | 14 ++++------- drivers/hwmon/aspeed-pwm-tacho.c | 27 +++++++++++++++++++--- 2 files changed, 29 insertions(+), 12 deletions(-) -- 2.14.1 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
