Expose the PMU on OMAP5. Signed-off-by: Nathan Lynch <nathan_lynch@xxxxxxxxxx> --- Notes: Briefly tested with perf on OMAP5 UEVM with next-20140124. arch/arm/boot/dts/omap5.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi index a72813a9663e..fbf4661436e2 100644 --- a/arch/arm/boot/dts/omap5.dtsi +++ b/arch/arm/boot/dts/omap5.dtsi @@ -76,6 +76,12 @@ <GIC_PPI 10 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>; }; + pmu { + compatible = "arm,cortex-a15-pmu"; + interrupts = <0 131 4>, + <0 132 4>; + }; + gic: interrupt-controller@48211000 { compatible = "arm,cortex-a15-gic"; interrupt-controller; -- 1.8.3.1 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html