We created the pingrp macros in imx6sl-pingrp.h for purpose of less LOC
when same pin group is used by multiple boards. However, DT maintainers
take it as an abuse of DTC macro support. So let's get rid of it to
make the pins used by given device more intuitive.
Signed-off-by: Shawn Guo <shawn.guo@xxxxxxxxxx>
---
arch/arm/boot/dts/imx6sl-evk.dts | 120 ++++++++++++++++++++++++++----
arch/arm/boot/dts/imx6sl-pingrp.h | 148 -------------------------------------
arch/arm/boot/dts/imx6sl.dtsi | 1 -
3 files changed, 107 insertions(+), 162 deletions(-)
delete mode 100644 arch/arm/boot/dts/imx6sl-pingrp.h
diff --git a/arch/arm/boot/dts/imx6sl-evk.dts b/arch/arm/boot/dts/imx6sl-evk.dts
index f5e4513..8594d13 100644
--- a/arch/arm/boot/dts/imx6sl-evk.dts
+++ b/arch/arm/boot/dts/imx6sl-evk.dts
@@ -86,55 +86,149 @@
};
pinctrl_ecspi1: ecspi1grp {
- fsl,pins = <MX6SL_ECSPI1_PINGRP1>;
+ fsl,pins = <
+ MX6SL_PAD_ECSPI1_MISO__ECSPI1_MISO 0x100b1
+ MX6SL_PAD_ECSPI1_MOSI__ECSPI1_MOSI 0x100b1
+ MX6SL_PAD_ECSPI1_SCLK__ECSPI1_SCLK 0x100b1
+ >;
};
pinctrl_fec: fecgrp {
- fsl,pins = <MX6SL_FEC_PINGRP1>;
+ fsl,pins = <
+ MX6SL_PAD_FEC_MDC__FEC_MDC 0x1b0b0
+ MX6SL_PAD_FEC_MDIO__FEC_MDIO 0x1b0b0
+ MX6SL_PAD_FEC_CRS_DV__FEC_RX_DV 0x1b0b0
+ MX6SL_PAD_FEC_RXD0__FEC_RX_DATA0 0x1b0b0
+ MX6SL_PAD_FEC_RXD1__FEC_RX_DATA1 0x1b0b0
+ MX6SL_PAD_FEC_TX_EN__FEC_TX_EN 0x1b0b0
+ MX6SL_PAD_FEC_TXD0__FEC_TX_DATA0 0x1b0b0
+ MX6SL_PAD_FEC_TXD1__FEC_TX_DATA1 0x1b0b0
+ MX6SL_PAD_FEC_REF_CLK__FEC_REF_OUT 0x4001b0a8
+ >;
};
pinctrl_uart1: uart1grp {
- fsl,pins = <MX6SL_UART1_PINGRP1>;
+ fsl,pins = <
+ MX6SL_PAD_UART1_RXD__UART1_RX_DATA 0x1b0b1
+ MX6SL_PAD_UART1_TXD__UART1_TX_DATA 0x1b0b1
+ >;
};
pinctrl_usbotg1: usbotg1grp {
- fsl,pins = <MX6SL_USBOTG1_PINGRP1>;
+ fsl,pins = <
+ MX6SL_PAD_EPDC_PWRCOM__USB_OTG1_ID 0x17059
+ >;
};
pinctrl_usdhc1: usdhc1grp {
- fsl,pins = <MX6SL_USDHC1_PINGRP_D8>;
+ fsl,pins = <
+ MX6SL_PAD_SD1_CMD__SD1_CMD 0x17059
+ MX6SL_PAD_SD1_CLK__SD1_CLK 0x10059
+ MX6SL_PAD_SD1_DAT0__SD1_DATA0 0x17059
+ MX6SL_PAD_SD1_DAT1__SD1_DATA1 0x17059
+ MX6SL_PAD_SD1_DAT2__SD1_DATA2 0x17059
+ MX6SL_PAD_SD1_DAT3__SD1_DATA3 0x17059
+ MX6SL_PAD_SD1_DAT4__SD1_DATA4 0x17059
+ MX6SL_PAD_SD1_DAT5__SD1_DATA5 0x17059
+ MX6SL_PAD_SD1_DAT6__SD1_DATA6 0x17059
+ MX6SL_PAD_SD1_DAT7__SD1_DATA7 0x17059
+ >;
};
pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
- fsl,pins = <MX6SL_USDHC1_PINGRP_D8_100MHZ>;
+ fsl,pins = <
+ MX6SL_PAD_SD1_CMD__SD1_CMD 0x170b9
+ MX6SL_PAD_SD1_CLK__SD1_CLK 0x100b9
+ MX6SL_PAD_SD1_DAT0__SD1_DATA0 0x170b9
+ MX6SL_PAD_SD1_DAT1__SD1_DATA1 0x170b9
+ MX6SL_PAD_SD1_DAT2__SD1_DATA2 0x170b9
+ MX6SL_PAD_SD1_DAT3__SD1_DATA3 0x170b9
+ MX6SL_PAD_SD1_DAT4__SD1_DATA4 0x170b9
+ MX6SL_PAD_SD1_DAT5__SD1_DATA5 0x170b9
+ MX6SL_PAD_SD1_DAT6__SD1_DATA6 0x170b9
+ MX6SL_PAD_SD1_DAT7__SD1_DATA7 0x170b9
+ >;
};
pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
- fsl,pins = <MX6SL_USDHC1_PINGRP_D8_200MHZ>;
+ fsl,pins = <
+ MX6SL_PAD_SD1_CMD__SD1_CMD 0x170f9
+ MX6SL_PAD_SD1_CLK__SD1_CLK 0x100f9
+ MX6SL_PAD_SD1_DAT0__SD1_DATA0 0x170f9
+ MX6SL_PAD_SD1_DAT1__SD1_DATA1 0x170f9
+ MX6SL_PAD_SD1_DAT2__SD1_DATA2 0x170f9
+ MX6SL_PAD_SD1_DAT3__SD1_DATA3 0x170f9
+ MX6SL_PAD_SD1_DAT4__SD1_DATA4 0x170f9
+ MX6SL_PAD_SD1_DAT5__SD1_DATA5 0x170f9
+ MX6SL_PAD_SD1_DAT6__SD1_DATA6 0x170f9
+ MX6SL_PAD_SD1_DAT7__SD1_DATA7 0x170f9
+ >;
};
pinctrl_usdhc2: usdhc2grp {
- fsl,pins = <MX6SL_USDHC2_PINGRP_D4>;
+ fsl,pins = <
+ MX6SL_PAD_SD2_CMD__SD2_CMD 0x17059
+ MX6SL_PAD_SD2_CLK__SD2_CLK 0x10059
+ MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x17059
+ MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x17059
+ MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x17059
+ MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x17059
+ >;
};
pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
- fsl,pins = <MX6SL_USDHC2_PINGRP_D4_100MHZ>;
+ fsl,pins = <
+ MX6SL_PAD_SD2_CMD__SD2_CMD 0x170b9
+ MX6SL_PAD_SD2_CLK__SD2_CLK 0x100b9
+ MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x170b9
+ MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x170b9
+ MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x170b9
+ MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x170b9
+ >;
};
pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
- fsl,pins = <MX6SL_USDHC2_PINGRP_D4_200MHZ>;
+ fsl,pins = <
+ MX6SL_PAD_SD2_CMD__SD2_CMD 0x170f9
+ MX6SL_PAD_SD2_CLK__SD2_CLK 0x100f9
+ MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x170f9
+ MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x170f9
+ MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x170f9
+ MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x170f9
+ >;
};
pinctrl_usdhc3: usdhc3grp {
- fsl,pins = <MX6SL_USDHC3_PINGRP_D4>;
+ fsl,pins = <
+ MX6SL_PAD_SD3_CMD__SD3_CMD 0x17059
+ MX6SL_PAD_SD3_CLK__SD3_CLK 0x10059
+ MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x17059
+ MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x17059
+ MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x17059
+ MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x17059
+ >;
};
pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
- fsl,pins = <MX6SL_USDHC3_PINGRP_D4_100MHZ>;
+ fsl,pins = <
+ MX6SL_PAD_SD3_CMD__SD3_CMD 0x170b9
+ MX6SL_PAD_SD3_CLK__SD3_CLK 0x100b9
+ MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x170b9
+ MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x170b9
+ MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x170b9
+ MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x170b9
+ >;
};
pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
- fsl,pins = <MX6SL_USDHC3_PINGRP_D4_200MHZ>;
+ fsl,pins = <
+ MX6SL_PAD_SD3_CMD__SD3_CMD 0x170f9
+ MX6SL_PAD_SD3_CLK__SD3_CLK 0x100f9
+ MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x170f9
+ MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x170f9
+ MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x170f9
+ MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x170f9
+ >;
};
};
};
diff --git a/arch/arm/boot/dts/imx6sl-pingrp.h b/arch/arm/boot/dts/imx6sl-pingrp.h
deleted file mode 100644
index ead26d4..0000000
--- a/arch/arm/boot/dts/imx6sl-pingrp.h
+++ /dev/null
@@ -1,148 +0,0 @@
-/*
- * Copyright (C) 2013 Freescale Semiconductor, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- */
-
-#ifndef __DTS_IMX6SL_PINGRP_H
-#define __DTS_IMX6SL_PINGRP_H
-
-#define MX6SL_ECSPI1_PINGRP1 \
- MX6SL_PAD_ECSPI1_MISO__ECSPI1_MISO 0x100b1 \
- MX6SL_PAD_ECSPI1_MOSI__ECSPI1_MOSI 0x100b1 \
- MX6SL_PAD_ECSPI1_SCLK__ECSPI1_SCLK 0x100b1
-
-#define MX6SL_FEC_PINGRP1 \
- MX6SL_PAD_FEC_MDC__FEC_MDC 0x1b0b0 \
- MX6SL_PAD_FEC_MDIO__FEC_MDIO 0x1b0b0 \
- MX6SL_PAD_FEC_CRS_DV__FEC_RX_DV 0x1b0b0 \
- MX6SL_PAD_FEC_RXD0__FEC_RX_DATA0 0x1b0b0 \
- MX6SL_PAD_FEC_RXD1__FEC_RX_DATA1 0x1b0b0 \
- MX6SL_PAD_FEC_TX_EN__FEC_TX_EN 0x1b0b0 \
- MX6SL_PAD_FEC_TXD0__FEC_TX_DATA0 0x1b0b0 \
- MX6SL_PAD_FEC_TXD1__FEC_TX_DATA1 0x1b0b0 \
- MX6SL_PAD_FEC_REF_CLK__FEC_REF_OUT 0x4001b0a8
-
-#define MX6SL_UART1_PINGRP1 \
- MX6SL_PAD_UART1_RXD__UART1_RX_DATA 0x1b0b1 \
- MX6SL_PAD_UART1_TXD__UART1_TX_DATA 0x1b0b1
-
-#define MX6SL_USBOTG1_PINGRP1 \
- MX6SL_PAD_EPDC_PWRCOM__USB_OTG1_ID 0x17059
-
-#define MX6SL_USBOTG1_PINGRP2 \
- MX6SL_PAD_FEC_RXD0__USB_OTG1_ID 0x17059
-
-#define MX6SL_USBOTG1_PINGRP3 \
- MX6SL_PAD_LCD_DAT1__USB_OTG1_ID 0x17059
-
-#define MX6SL_USBOTG1_PINGRP4 \
- MX6SL_PAD_REF_CLK_32K__USB_OTG1_ID 0x17059
-
-#define MX6SL_USBOTG1_PINGRP5 \
- MX6SL_PAD_SD3_DAT0__USB_OTG1_ID 0x17059
-
-#define MX6SL_USBOTG2_PINGRP1 \
- MX6SL_PAD_ECSPI1_SCLK__USB_OTG2_OC 0x17059
-
-#define MX6SL_USBOTG2_PINGRP2 \
- MX6SL_PAD_ECSPI2_SCLK__USB_OTG2_OC 0x17059
-
-#define MX6SL_USBOTG2_PINGRP3 \
- MX6SL_PAD_KEY_ROW5__USB_OTG2_OC 0x17059
-
-#define MX6SL_USBOTG2_PINGRP4 \
- MX6SL_PAD_SD3_DAT2__USB_OTG2_OC 0x17059
-
-#define MX6SL_USDHC1_D4(pad, pad_data3, pad_clk) \
- MX6SL_PAD_SD1_CMD__SD1_CMD pad \
- MX6SL_PAD_SD1_CLK__SD1_CLK pad_clk \
- MX6SL_PAD_SD1_DAT0__SD1_DATA0 pad \
- MX6SL_PAD_SD1_DAT1__SD1_DATA1 pad \
- MX6SL_PAD_SD1_DAT2__SD1_DATA2 pad \
- MX6SL_PAD_SD1_DAT3__SD1_DATA3 pad_data3
-
-#define MX6SL_USDHC1_D8(pad, pad_data3, pad_clk) \
- MX6SL_USDHC1_D4(pad, pad_data3, pad_clk) \
- MX6SL_PAD_SD1_DAT4__SD1_DATA4 pad \
- MX6SL_PAD_SD1_DAT5__SD1_DATA5 pad \
- MX6SL_PAD_SD1_DAT6__SD1_DATA6 pad \
- MX6SL_PAD_SD1_DAT7__SD1_DATA7 pad
-
-#define MX6SL_USDHC2_D4(pad, pad_data3, pad_clk) \
- MX6SL_PAD_SD2_CMD__SD2_CMD pad \
- MX6SL_PAD_SD2_CLK__SD2_CLK pad_clk \
- MX6SL_PAD_SD2_DAT0__SD2_DATA0 pad \
- MX6SL_PAD_SD2_DAT1__SD2_DATA1 pad \
- MX6SL_PAD_SD2_DAT2__SD2_DATA2 pad \
- MX6SL_PAD_SD2_DAT3__SD2_DATA3 pad_data3
-
-#define MX6SL_USDHC2_D8(pad, pad_data3, pad_clk) \
- MX6SL_USDHC2_D4(pad, pad_data3, pad_clk) \
- MX6SL_PAD_SD2_DAT4__SD2_DATA4 pad \
- MX6SL_PAD_SD2_DAT5__SD2_DATA5 pad \
- MX6SL_PAD_SD2_DAT6__SD2_DATA6 pad \
- MX6SL_PAD_SD2_DAT7__SD2_DATA7 pad
-
-#define MX6SL_USDHC3_D4(pad, pad_data3, pad_clk) \
- MX6SL_PAD_SD3_CMD__SD3_CMD pad \
- MX6SL_PAD_SD3_CLK__SD3_CLK pad_clk \
- MX6SL_PAD_SD3_DAT0__SD3_DATA0 pad \
- MX6SL_PAD_SD3_DAT1__SD3_DATA1 pad \
- MX6SL_PAD_SD3_DAT2__SD3_DATA2 pad \
- MX6SL_PAD_SD3_DAT3__SD3_DATA3 pad_data3
-
-#define MX6SL_USDHC3_D8(pad, pad_data3, pad_clk) \
- MX6SL_USDHC3_D4(pad, pad_data3, pad_clk) \
- MX6SL_PAD_SD2_DAT4__SD3_DATA4 pad \
- MX6SL_PAD_SD2_DAT5__SD3_DATA5 pad \
- MX6SL_PAD_SD2_DAT6__SD3_DATA6 pad \
- MX6SL_PAD_SD2_DAT7__SD3_DATA7 pad
-
-#define MX6SL_USDHC4_D4(pad, pad_data3, pad_clk) \
- MX6SL_PAD_EPDC_BDR1__SD4_CMD pad \
- MX6SL_PAD_EPDC_BDR0__SD4_CLK pad_clk \
- MX6SL_PAD_EPDC_PWRCOM__SD4_DATA0 pad \
- MX6SL_PAD_EPDC_PWRINT__SD4_DATA1 pad \
- MX6SL_PAD_EPDC_PWRSTAT__SD4_DATA2 pad \
- MX6SL_PAD_EPDC_PWRWAKEUP__SD4_DATA3 pad_data3
-
-#define MX6SL_USDHC4_D8(pad, pad_data3, pad_clk) \
- MX6SL_USDHC4_D4(pad, pad_data3, pad_clk) \
- MX6SL_PAD_KEY_COL7__SD4_DATA4 pad \
- MX6SL_PAD_KEY_ROW7__SD4_DATA5 pad \
- MX6SL_PAD_KEY_COL3__SD4_DATA6 pad \
- MX6SL_PAD_KEY_ROW3__SD4_DATA7 pad
-
-#define MX6SL_USDHC1_PINGRP_D4 MX6SL_USDHC1_D4(0x17059, 0x17059, 0x10059)
-#define MX6SL_USDHC1_PINGRP_D4_100MHZ MX6SL_USDHC1_D4(0x170b9, 0x170b9, 0x100b9)
-#define MX6SL_USDHC1_PINGRP_D4_200MHZ MX6SL_USDHC1_D4(0x170f9, 0x170f9, 0x100f9)
-#define MX6SL_USDHC1_PINGRP_D8 MX6SL_USDHC1_D8(0x17059, 0x17059, 0x10059)
-#define MX6SL_USDHC1_PINGRP_D8_100MHZ MX6SL_USDHC1_D8(0x170b9, 0x170b9, 0x100b9)
-#define MX6SL_USDHC1_PINGRP_D8_200MHZ MX6SL_USDHC1_D8(0x170f9, 0x170f9, 0x100f9)
-
-#define MX6SL_USDHC2_PINGRP_D4 MX6SL_USDHC2_D4(0x17059, 0x17059, 0x10059)
-#define MX6SL_USDHC2_PINGRP_D4_100MHZ MX6SL_USDHC2_D4(0x170b9, 0x170b9, 0x100b9)
-#define MX6SL_USDHC2_PINGRP_D4_200MHZ MX6SL_USDHC2_D4(0x170f9, 0x170f9, 0x100f9)
-#define MX6SL_USDHC2_PINGRP_D8 MX6SL_USDHC2_D8(0x17059, 0x17059, 0x10059)
-#define MX6SL_USDHC2_PINGRP_D8_100MHZ MX6SL_USDHC2_D8(0x170b9, 0x170b9, 0x100b9)
-#define MX6SL_USDHC2_PINGRP_D8_200MHZ MX6SL_USDHC2_D8(0x170f9, 0x170f9, 0x100f9)
-
-#define MX6SL_USDHC3_PINGRP_D4 MX6SL_USDHC3_D4(0x17059, 0x17059, 0x10059)
-#define MX6SL_USDHC3_PINGRP_D4_100MHZ MX6SL_USDHC3_D4(0x170b9, 0x170b9, 0x100b9)
-#define MX6SL_USDHC3_PINGRP_D4_200MHZ MX6SL_USDHC3_D4(0x170f9, 0x170f9, 0x100f9)
-#define MX6SL_USDHC3_PINGRP_D8 MX6SL_USDHC3_D8(0x17059, 0x17059, 0x10059)
-#define MX6SL_USDHC3_PINGRP_D8_100MHZ MX6SL_USDHC3_D8(0x170b9, 0x170b9, 0x100b9)
-#define MX6SL_USDHC3_PINGRP_D8_200MHZ MX6SL_USDHC3_D8(0x170f9, 0x170f9, 0x100f9)
-
-#define MX6SL_USDHC4_PINGRP_D4 MX6SL_USDHC4_D4(0x17059, 0x17059, 0x10059)
-#define MX6SL_USDHC4_PINGRP_D4_100MHZ MX6SL_USDHC4_D4(0x170b9, 0x170b9, 0x100b9)
-#define MX6SL_USDHC4_PINGRP_D4_200MHZ MX6SL_USDHC4_D4(0x170f9, 0x170f9, 0x100f9)
-#define MX6SL_USDHC4_PINGRP_D8 MX6SL_USDHC4_D8(0x17059, 0x17059, 0x10059)
-#define MX6SL_USDHC4_PINGRP_D8_100MHZ MX6SL_USDHC4_D8(0x170b9, 0x170b9, 0x100b9)
-#define MX6SL_USDHC4_PINGRP_D8_200MHZ MX6SL_USDHC4_D8(0x170f9, 0x170f9, 0x100f9)
-
-#endif /* __DTS_IMX6SL_PINGRP_H */
diff --git a/arch/arm/boot/dts/imx6sl.dtsi b/arch/arm/boot/dts/imx6sl.dtsi
index 2ed687c..2b7641a 100644
--- a/arch/arm/boot/dts/imx6sl.dtsi
+++ b/arch/arm/boot/dts/imx6sl.dtsi
@@ -10,7 +10,6 @@
#include <dt-bindings/interrupt-controller/irq.h>
#include "skeleton.dtsi"
#include "imx6sl-pinfunc.h"
-#include "imx6sl-pingrp.h"
#include <dt-bindings/clock/imx6sl-clock.h>
/ {
--
1.7.9.5
--
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