On Sat, Sep 09, 2017 at 08:32:41PM +0200, Lukas Wunner wrote: > All chips supported by this driver clock data out on the falling edge > and latch data in on the rising edge, hence SPI mode (0,0) or (1,1) > must be used. > > Furthermore, none of the chips has an internal reference voltage > regulator, so an external supply is always required and needs to be > specified in the device tree lest the IIO "scale" in sysfs cannot be > calculated. > > Document these requirements in the device tree binding, add compatible > strings for the newly supported mcp3550/1/3 and explain that SPI mode > (0,0) should be preferred for these chips. > > Cc: Mathias Duckeck <m.duckeck@xxxxxxxxx> > Signed-off-by: Lukas Wunner <lukas@xxxxxxxxx> > --- > Changes since v1: > - Move support for continuous conversion mode to separate patch > which is marked informational / not for merging. (Rob, Jonathan) > > Documentation/devicetree/bindings/iio/adc/mcp320x.txt | 14 ++++++++++++++ > 1 file changed, 14 insertions(+) Acked-by: Rob Herring <robh@xxxxxxxxxx> -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
