On 2017/9/6 17:59, Jean-Philippe Brucker wrote: > On 06/09/17 02:16, Yisheng Xie wrote: >> Hi Jean-Philippe, >> >> On 2017/9/5 20:56, Jean-Philippe Brucker wrote: >>> On 31/08/17 09:20, Yisheng Xie wrote: >>>> Jean-Philippe has post a patchset for Adding PCIe SVM support to ARM SMMUv3: >>>> https://www.spinics.net/lists/arm-kernel/msg565155.html >>>> >>>> But for some platform devices(aka on-chip integrated devices), there is also >>>> SVM requirement, which works based on the SMMU stall mode. >>>> Jean-Philippe has prepared a prototype patchset to support it: >>>> git://linux-arm.org/linux-jpb.git svm/stall >>> >>> Only meant for testing at that point, and unfit even for an RFC. >> >> Sorry about that, I should ask you before send it out. It's my mistake. For I also >> have some question about this patchset. >> >> We have related device, and would like to do some help about it. Do you have >> any plan about upstream ? >> >>> >>>> We tested this patchset with some fixes on a on-chip integrated device. The >>>> basic function is ok, so I just send them out for review, although this >>>> patchset heavily depends on the former patchset (PCIe SVM support for ARM >>>> SMMUv3), which is still under discussion. >>>> >>>> Patch Overview: >>>> *1 to 3 prepare for device tree or acpi get the device stall ability and pasid bits >>>> *4 is to realise the SVM function for platform device >>>> *5 is fix a bug when test SVM function while SMMU donnot support this feature >>>> *6 avoid ILLEGAL setting of STE and CD entry about stall >>>> >>>> Acctually here, I also have some questions about SVM on SMMUv3: >>>> >>>> 1. Why the SVM feature on SMMUv3 depends on BTM feature? when bind a task to device, >>>> it will register a mmu_notify. Therefore, when a page range is invalid, we can >>>> send TLBI or ATC invalid without BTM? >>> >>> We could, but the end goal for SVM is to perfectly mirror the CPU page >>> tables. So for platform SVM we would like to get rid of MMU notifiers >>> entirely. >> >> I see, but for some SMMU which do not support BTM, it cannot benefit from SVM. >> >> Meanwhile, do you mean even with BTM feature, the PCI-e device also need to send a >> ATC invalid by MMU notify? It seems not fair, why not hardware do the entirely work >> in this case? It may costly for send ATC invalid and sync. > > It will certainly be costly. But there are major problems with > transforming broadcast TLB maintenance into ATC invalidations in HW: > > * VMID:ASID to SID:SSID conversion. TLBIs use VMID:ASID, while ATCIs use > SID:SSID. > > * Most importantly, ATC invalidations accounting. Each endpoint has a > limited number of in-flight ATC invalidate requests. The conversion module > would have to buffer incoming invalidations and wait for in-flight ATC > invalidation to complete before sending the next ones. In case of > overflow, either we lose invalidation (which opens security holes) or we > somehow put back-pressure on the interconnect (no idea how feasible this > is, I suspect really hard). > > Solving the last one is also quite difficult in software, but at least we > can still invalidate a range. In hardware we would invalidate the ATC > page-by-page and quickly jam the bus. > Speak to the invalidation, I have one more question. There is a time window between 1) modify page table; 2) tlb invalidate; ARM-CPU Device 1. modify page table ^^^^^ Can still write data through smmu tlb even page table was already modified. (At this point, the same virtual addr may not point to the same thing for CPU and device!!! I'm afraid there may be some data-loss or other potential problems if this situation happens.) 2. tlb invalidate range -- Thanks, Bob -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
