On am33xx we're missing the pmu and emif nodes with their related
"ti,hwmods" properties that the SoC interconnect code needs.
Note that this will only show up as a bug with "doesn't have
mpu register target base" boot errors when the legacy platform
data is removed.
Let's also update the related binding documentation while at it.
Signed-off-by: Tony Lindgren <tony@xxxxxxxxxxx>
---
.../devicetree/bindings/memory-controllers/ti/emif.txt | 6 ++++--
arch/arm/boot/dts/am33xx.dtsi | 10 +++++++++-
2 files changed, 13 insertions(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/memory-controllers/ti/emif.txt b/Documentation/devicetree/bindings/memory-controllers/ti/emif.txt
--- a/Documentation/devicetree/bindings/memory-controllers/ti/emif.txt
+++ b/Documentation/devicetree/bindings/memory-controllers/ti/emif.txt
@@ -7,8 +7,10 @@ of the EMIF IP and memory parts attached to it.
Required properties:
- compatible : Should be of the form "ti,emif-<ip-rev>" where <ip-rev>
- is the IP revision of the specific EMIF instance.
- For am437x should be ti,emif-am4372.
+ is the IP revision of the specific EMIF instance. For newer controllers,
+ compatible should be one of the following:
+ "ti,emif-am3352"
+ "ti,emif-am4372"
- phy-type : <u32> indicating the DDR phy type. Following are the
allowed values
diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi
--- a/arch/arm/boot/dts/am33xx.dtsi
+++ b/arch/arm/boot/dts/am33xx.dtsi
@@ -128,9 +128,11 @@
};
};
- pmu {
+ pmu@4b000000 {
compatible = "arm,cortex-a8-pmu";
interrupts = <3>;
+ reg = <0x4b000000 0x1000000>;
+ ti,hwmods = "debugss";
};
/*
@@ -927,6 +929,12 @@
};
};
+ emif: emif@4c000000 {
+ compatible = "ti,emif-am3352";
+ reg = <0x4c000000 0x1000000>;
+ ti,hwmods = "emif";
+ };
+
gpmc: gpmc@50000000 {
compatible = "ti,am3352-gpmc";
ti,hwmods = "gpmc";
--
2.14.1
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