On Wed, Aug 16, 2017 at 10:20:51AM +0530, Vignesh R wrote: > Cadence QSPI IP has a adapted loop-back circuit which can be enabled by > setting BYPASS field to 0 in READCAPTURE register. It enables use of > QSPI return clock to latch the data rather than the internal QSPI > reference clock. For high speed operations, adapted loop-back circuit > using QSPI return clock helps to increase data valid window. > > Add DT parameter cdns,rclk-en to help enable adapted loop-back circuit > for boards which do have QSPI return clock provided. Update binding > documentation for the same. > > Signed-off-by: Vignesh R <vigneshr@xxxxxx> > --- > Documentation/devicetree/bindings/mtd/cadence-quadspi.txt | 3 +++ > 1 file changed, 3 insertions(+) Acked-by: Rob Herring <robh@xxxxxxxxxx> -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
