Some SoC implementations that use this controller have a reduced pin
count so the meaning of "full" and "half" with change.
Signed-off-by: Chris Packham <chris.packham@xxxxxxxxxxxxxxxxxxx>
---
.../bindings/memory-controllers/mvebu-sdram-controller.txt | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/Documentation/devicetree/bindings/memory-controllers/mvebu-sdram-controller.txt b/Documentation/devicetree/bindings/memory-controllers/mvebu-sdram-controller.txt
index 89657d1d4cd4..3041868321c8 100644
--- a/Documentation/devicetree/bindings/memory-controllers/mvebu-sdram-controller.txt
+++ b/Documentation/devicetree/bindings/memory-controllers/mvebu-sdram-controller.txt
@@ -13,6 +13,12 @@ Required properties:
- reg: a resource specifier for the register space, which should
include all SDRAM controller registers as per the datasheet.
+Optional properties:
+ - marvell,reduced-width: some SoCs that use this SDRAM controller have
+ a reduced pin count. On such systems "full" width is 32-bits and
+ "half" width is 16-bits. Set this property to indicate that the SoC
+ used is such a system.
+
Example:
sdramc@1400 {
--
2.13.0
--
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