> -----Original Message-----
> From: Wood Scott-B07421
> Sent: 2014年1月18日 星期六 9:06
> To: Tang Yuantian-B29983
> Cc: Wood Scott-B07421; galak@xxxxxxxxxxxxxxxxxxx; mark.rutland@xxxxxxx;
> devicetree@xxxxxxxxxxxxxxx; linuxppc-dev@xxxxxxxxxxxxxxxx; Li Yang-Leo-
> R58472
> Subject: Re: [PATCH v9] clk: corenet: Adds the clock binding
>
> On Mon, 2014-01-13 at 16:16 +0800, Tang Yuantian wrote:
> > +Example for clock block and clock provider:
> > +/ {
> > + clockgen: global-utilities@e1000 {
> > + compatible = "fsl,p5020-clockgen", "fsl,qoriq-clockgen-1.0";
> > + ranges = <0x0 0xe1000 0x1000>;
> > + clock-frequency = 133333;
>
> Missing <> around 133333, and the actual p5020ds input clock (based on
> observing what U-Boot fills in) is 133333333, not 133333.
>
Sorry, :(
> I'll fix when applying.
>
Thank you very much.
Regards,
Yuantian
> -Scott
>
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