The clock controller provides a few reset lines as well. Add the
corresponding CPU cores.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@xxxxxxxxxxxxxx>
Reviewed-by: Neil Armstrong <narmstrong@xxxxxxxxxxxx>
---
arch/arm/boot/dts/meson8.dtsi | 1 +
arch/arm/boot/dts/meson8b.dtsi | 1 +
2 files changed, 2 insertions(+)
diff --git a/arch/arm/boot/dts/meson8.dtsi b/arch/arm/boot/dts/meson8.dtsi
index 6fe6a159e960..b98d44fde6b6 100644
--- a/arch/arm/boot/dts/meson8.dtsi
+++ b/arch/arm/boot/dts/meson8.dtsi
@@ -168,6 +168,7 @@
&cbus {
clkc: clock-controller@4000 {
#clock-cells = <1>;
+ #reset-cells = <1>;
compatible = "amlogic,meson8-clkc";
reg = <0x8000 0x4>, <0x4000 0x460>;
};
diff --git a/arch/arm/boot/dts/meson8b.dtsi b/arch/arm/boot/dts/meson8b.dtsi
index 8fce13844b0c..bc278da7df0d 100644
--- a/arch/arm/boot/dts/meson8b.dtsi
+++ b/arch/arm/boot/dts/meson8b.dtsi
@@ -119,6 +119,7 @@
&cbus {
clkc: clock-controller@4000 {
#clock-cells = <1>;
+ #reset-cells = <1>;
compatible = "amlogic,meson8b-clkc";
reg = <0x8000 0x4>, <0x4000 0x460>;
};
--
2.13.3
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