On Mon, Jul 24, 2017 at 09:58:56PM +0800, Chen-Yu Tsai wrote: > Starting with the A83T SoC, Allwinner introduced a new timing mode for > its MMC clocks. The new mode changes how the MMC controller sample and > output clocks are delayed to match chip and board specifics. There are > two controls for this, one on the CCU side controlling how the clocks > behave, and one in the MMC controller controlling what inputs to take > and how to route them. > > In the old mode, the MMC clock had 2 child clocks providing the output > and sample clocks, which could be delayed by a number of clock cycles > measured from the MMC clock's parent. > > With the new mode, the 2 delay clocks are no longer active. Instead, > the delays and associated controls are moved into the MMC controller. > The output of the MMC clock is also halved. > > The difference in how things are wired between the modes means that the > clock controls and the MMC controls must match. To achieve this in a > clear, explicit way, we introduce two functions for the MMC driver to > use: one queries the hardware for the current mode set, and the other > allows the MMC driver to request a mode. > > Signed-off-by: Chen-Yu Tsai <wens@xxxxxxxx> Acked-by: Maxime Ripard <maxime.ripard@xxxxxxxxxxxxxxxxxx> Thanks! Maxime -- Maxime Ripard, Free Electrons Embedded Linux and Kernel engineering http://free-electrons.com
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