This patch is our first proposal to address the need for a suitable ECC devicetree binding. NAND controllers have special ECC modes, raising per-driver ECC mode devicetree binding. See for instance the binding for OMAP: - ti,nand-ecc-opt: A string setting the ECC layout to use. One of: "sw" <deprecated> use "ham1" instead "hw" <deprecated> use "ham1" instead "hw-romcode" <deprecated> use "ham1" instead "ham1" 1-bit Hamming ecc code "bch4" 4-bit BCH ecc code "bch8" 8-bit BCH ecc code Other drivers (such as pxa3xx-nand) have similar requirements, with special (controller-specific) ECC modes. Instead of adding a possibly different binding per compatible-string, let's add generic ECC strength and ECC step size. This properties should describe completely the ECC mode and let drivers choose the appropriate ECC mode. Ezequiel Garcia (1): mtd: nand: Add a devicetree binding for ECC strength and ECC step size Documentation/devicetree/bindings/mtd/nand.txt | 4 ++++ 1 file changed, 4 insertions(+) -- 1.8.1.5 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
