On Thu, Jul 20, 2017 at 11:44:47AM +0800, Chen-Yu Tsai wrote: > The MMC controller can support DDR52 transfers under the new timing > mode. According to the BSP kernel, the module clock has to be double > the card clock, regardless of the bus width. The default timings in > the hardware can be used. > > This also reworks the code setting the internal divider, getting rid > of a extra conditional. > > Signed-off-by: Chen-Yu Tsai <wens@xxxxxxxx> Acked-by: Maxime Ripard <maxime.ripard@xxxxxxxxxxxxxxxxxx> Thanks! Maxime -- Maxime Ripard, Free Electrons Embedded Linux and Kernel engineering http://free-electrons.com
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