Hi Moritz, [auto build test WARNING on net-next/master] [also build test WARNING on v4.12 next-20170713] [if your patch is applied to the wrong git tree, please drop us a note to help improve the system] url: https://github.com/0day-ci/linux/commits/Moritz-Fischer/dt-bindings-net-Add-bindings-for-National-Instruments-XGE-netdev/20170714-125718 config: ia64-allmodconfig (attached as .config) compiler: ia64-linux-gcc (GCC) 6.2.0 reproduce: wget https://raw.githubusercontent.com/01org/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross chmod +x ~/bin/make.cross # save the attached .config to linux build tree make.cross ARCH=ia64 All warnings (new ones prefixed by >>): In file included from include/linux/if_ether.h:23:0, from include/linux/etherdevice.h:25, from drivers/net/ethernet/ni/nixge.c:14: drivers/net/ethernet/ni/nixge.c: In function 'nixge_dma_bd_release': >> drivers/net/ethernet/ni/nixge.c:241:17: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] dev_kfree_skb((struct sk_buff *) ^ include/linux/skbuff.h:977:38: note: in definition of macro 'dev_kfree_skb' #define dev_kfree_skb(a) consume_skb(a) ^ drivers/net/ethernet/ni/nixge.c: In function 'nixge_dma_bd_init': >> drivers/net/ethernet/ni/nixge.c:299:35: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast] priv->rx_bd_v[i].sw_id_offset = (u32)skb; ^ drivers/net/ethernet/ni/nixge.c: In function 'nixge_start_xmit_done': drivers/net/ethernet/ni/nixge.c:452:22: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] dev_kfree_skb_irq((struct sk_buff *)cur_p->app4); ^ drivers/net/ethernet/ni/nixge.c: In function 'nixge_recv': drivers/net/ethernet/ni/nixge.c:546:9: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] skb = (struct sk_buff *)(cur_p->sw_id_offset); ^ drivers/net/ethernet/ni/nixge.c:577:25: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast] cur_p->sw_id_offset = (u32)new_skb; ^ drivers/net/ethernet/ni/nixge.c: In function 'nixge_dma_err_handler': drivers/net/ethernet/ni/nixge.c:687:22: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] dev_kfree_skb_irq((struct sk_buff *)cur_p->app4); ^ vim +241 drivers/net/ethernet/ni/nixge.c 228 229 #define nixge_ctrl_poll_timeout(priv, addr, val, cond, sleep_us, timeout_us) \ 230 readl_poll_timeout((priv)->ctrl_regs + (addr), (val), cond, \ 231 (sleep_us), (timeout_us)) 232 233 static void nixge_dma_bd_release(struct net_device *ndev) 234 { 235 int i; 236 struct nixge_priv *priv = netdev_priv(ndev); 237 238 for (i = 0; i < RX_BD_NUM; i++) { 239 dma_unmap_single(ndev->dev.parent, priv->rx_bd_v[i].phys, 240 priv->max_frm_size, DMA_FROM_DEVICE); > 241 dev_kfree_skb((struct sk_buff *) 242 (priv->rx_bd_v[i].sw_id_offset)); 243 } 244 245 if (priv->rx_bd_v) { 246 dma_free_coherent(ndev->dev.parent, 247 sizeof(*priv->rx_bd_v) * RX_BD_NUM, 248 priv->rx_bd_v, 249 priv->rx_bd_p); 250 } 251 if (priv->tx_bd_v) { 252 dma_free_coherent(ndev->dev.parent, 253 sizeof(*priv->tx_bd_v) * TX_BD_NUM, 254 priv->tx_bd_v, 255 priv->tx_bd_p); 256 } 257 } 258 259 static int nixge_dma_bd_init(struct net_device *ndev) 260 { 261 u32 cr; 262 int i; 263 struct sk_buff *skb; 264 struct nixge_priv *priv = netdev_priv(ndev); 265 266 /* Reset the indexes which are used for accessing the BDs */ 267 priv->tx_bd_ci = 0; 268 priv->tx_bd_tail = 0; 269 priv->rx_bd_ci = 0; 270 271 /* Allocate the Tx and Rx buffer descriptors. */ 272 priv->tx_bd_v = dma_zalloc_coherent(ndev->dev.parent, 273 sizeof(*priv->tx_bd_v) * TX_BD_NUM, 274 &priv->tx_bd_p, GFP_KERNEL); 275 if (!priv->tx_bd_v) 276 goto out; 277 278 priv->rx_bd_v = dma_zalloc_coherent(ndev->dev.parent, 279 sizeof(*priv->rx_bd_v) * RX_BD_NUM, 280 &priv->rx_bd_p, GFP_KERNEL); 281 if (!priv->rx_bd_v) 282 goto out; 283 284 for (i = 0; i < TX_BD_NUM; i++) { 285 priv->tx_bd_v[i].next = priv->tx_bd_p + 286 sizeof(*priv->tx_bd_v) * 287 ((i + 1) % TX_BD_NUM); 288 } 289 290 for (i = 0; i < RX_BD_NUM; i++) { 291 priv->rx_bd_v[i].next = priv->rx_bd_p + 292 sizeof(*priv->rx_bd_v) * 293 ((i + 1) % RX_BD_NUM); 294 295 skb = netdev_alloc_skb_ip_align(ndev, priv->max_frm_size); 296 if (!skb) 297 goto out; 298 > 299 priv->rx_bd_v[i].sw_id_offset = (u32)skb; 300 priv->rx_bd_v[i].phys = dma_map_single(ndev->dev.parent, 301 skb->data, 302 priv->max_frm_size, 303 DMA_FROM_DEVICE); 304 priv->rx_bd_v[i].cntrl = priv->max_frm_size; 305 } 306 307 /* Start updating the Rx channel control register */ 308 cr = nixge_dma_read_reg(priv, XAXIDMA_RX_CR_OFFSET); 309 /* Update the interrupt coalesce count */ 310 cr = ((cr & ~XAXIDMA_COALESCE_MASK) | 311 ((priv->coalesce_count_rx) << XAXIDMA_COALESCE_SHIFT)); 312 /* Update the delay timer count */ 313 cr = ((cr & ~XAXIDMA_DELAY_MASK) | 314 (XAXIDMA_DFT_RX_WAITBOUND << XAXIDMA_DELAY_SHIFT)); 315 /* Enable coalesce, delay timer and error interrupts */ 316 cr |= XAXIDMA_IRQ_ALL_MASK; 317 /* Write to the Rx channel control register */ 318 nixge_dma_write_reg(priv, XAXIDMA_RX_CR_OFFSET, cr); 319 320 /* Start updating the Tx channel control register */ 321 cr = nixge_dma_read_reg(priv, XAXIDMA_TX_CR_OFFSET); 322 /* Update the interrupt coalesce count */ 323 cr = (((cr & ~XAXIDMA_COALESCE_MASK)) | 324 ((priv->coalesce_count_tx) << XAXIDMA_COALESCE_SHIFT)); 325 /* Update the delay timer count */ 326 cr = (((cr & ~XAXIDMA_DELAY_MASK)) | 327 (XAXIDMA_DFT_TX_WAITBOUND << XAXIDMA_DELAY_SHIFT)); 328 /* Enable coalesce, delay timer and error interrupts */ 329 cr |= XAXIDMA_IRQ_ALL_MASK; 330 /* Write to the Tx channel control register */ 331 nixge_dma_write_reg(priv, XAXIDMA_TX_CR_OFFSET, cr); 332 333 /* Populate the tail pointer and bring the Rx Axi DMA engine out of 334 * halted state. This will make the Rx side ready for reception. 335 */ 336 nixge_dma_write_reg(priv, XAXIDMA_RX_CDESC_OFFSET, priv->rx_bd_p); 337 cr = nixge_dma_read_reg(priv, XAXIDMA_RX_CR_OFFSET); 338 nixge_dma_write_reg(priv, XAXIDMA_RX_CR_OFFSET, 339 cr | XAXIDMA_CR_RUNSTOP_MASK); 340 nixge_dma_write_reg(priv, XAXIDMA_RX_TDESC_OFFSET, priv->rx_bd_p + 341 (sizeof(*priv->rx_bd_v) * (RX_BD_NUM - 1))); 342 343 /* Write to the RS (Run-stop) bit in the Tx channel control register. 344 * Tx channel is now ready to run. But only after we write to the 345 * tail pointer register that the Tx channel will start transmitting. 346 */ 347 nixge_dma_write_reg(priv, XAXIDMA_TX_CDESC_OFFSET, priv->tx_bd_p); 348 cr = nixge_dma_read_reg(priv, XAXIDMA_TX_CR_OFFSET); 349 nixge_dma_write_reg(priv, XAXIDMA_TX_CR_OFFSET, 350 cr | XAXIDMA_CR_RUNSTOP_MASK); 351 352 return 0; 353 out: 354 nixge_dma_bd_release(ndev); 355 return -ENOMEM; 356 } 357 --- 0-DAY kernel test infrastructure Open Source Technology Center https://lists.01.org/pipermail/kbuild-all Intel Corporation
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