Hi Geert,
Thank you for review!
On 10.07.2017 11:20, Geert Uytterhoeven wrote:
On Fri, Jul 7, 2017 at 4:09 AM, Vladimir Barinov
<vladimir.barinov@xxxxxxxxxxxxxxxxxx> wrote:
From: Vladimir Barinov <vladimir.barinov+renesas@xxxxxxxxxxxxxxxxxx>
This enables I2C4 for ULCB board
Signed-off-by: Vladimir Barinov <vladimir.barinov+renesas@xxxxxxxxxxxxxxxxxx>
Reviewed-by: Geert Uytterhoeven <geert+renesas@xxxxxxxxx>
--- a/arch/arm64/boot/dts/renesas/ulcb.dtsi
+++ b/arch/arm64/boot/dts/renesas/ulcb.dtsi
@@ -189,6 +189,12 @@
};
};
+&i2c4 {
+ status = "okay";
+
+ clock-frequency = <400000>;
Is this a bus limitation, or a limitation for the VC6 that's added in a later
patch?
Yes, IDT VC5 clock generator supports up to 400kHz.
I've explicitly set 400kHz as default since the documentation says that
the default value is 100kHz if 'clock-frequency' not set:
Documentation/devicetree/bindings/i2c/i2c-rcar.txt
Regards,
Vladimir
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