On 19/06/2017 22:13, Florian Fainelli wrote:
> On 06/14/2017 09:29 AM, Phil Elwell wrote:
>> Devices in the BCM2835 AUX block share a common interrupt line, with a
>> register indicating which devices have active IRQs. Expose this as a
>> nested interrupt controller to avoid IRQ sharing problems (easily
>> observed if UART1 and SPI1/2 are enabled simultaneously).
>>
>> Signed-off-by: Phil Elwell <phil@xxxxxxxxxxxxxxx>
>> ---
>
>> +/*
>> + * The irq_mask and irq_unmask function pointers are used without
>> + * validity checks, so they must not be NULL. Create a dummy function
>> + * with the expected type for use as a no-op.
>> + */
>> +static void bcm2835_aux_irq_dummy(struct irq_data *data)
>> +{
>> +}
>> +
>> +static struct irq_chip bcm2835_aux_irq_chip = {
>> + .name = "bcm2835-aux_irq",
>> + .irq_mask = bcm2835_aux_irq_dummy,
>> + .irq_unmask = bcm2835_aux_irq_dummy,
>> +};
>
> So how are the interrupt enabled/disabled if this interrupt controller
> just returns their pending state?
Interrupts must be enabled, disabled and acknowledged on the blocks in the
AUX domain - UART1, SPI1 and SPI2. There is no additional masking -
AUXIRQ is essentially an interrupt sharing accelerator.
Phil
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