On Fri, Jun 09, 2017 at 03:10:41PM +0800, Mark Yao wrote: > For RK3399 HDMI, there is an external clock need for HDMI PHY, > and it should keep the same clock rate with VOP DCLK. > > VPLL have supported the clock for HDMI PHY, but there is no > clock divider bewteen VPLL and HDMI PHY. So we need to set the > VPLL rate manually in HDMI driver. > > Signed-off-by: Yakir Yang <ykk@xxxxxxxxxxxxxx> > Signed-off-by: Mark Yao <mark.yao@xxxxxxxxxxxxxx> > --- > Changes in v3: none > Changes in v2: describe vpll on Documentation. > > .../bindings/display/rockchip/dw_hdmi-rockchip.txt | 2 +- Acked-by: Rob Herring <robh@xxxxxxxxxx> > drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 25 +++++++++++++++++++++- > 2 files changed, 25 insertions(+), 2 deletions(-) -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
