On Sun, Jun 11, 2017 at 02:58:47PM +0800, icenowy@xxxxxxx wrote: > 在 2017-06-07 17:42,Maxime Ripard 写道: > > On Mon, Jun 05, 2017 at 12:01:48AM +0800, Icenowy Zheng wrote: > > > + soc { > > > + display_clocks: clock@1000000 { > > > + compatible = "allwinner,sun8i-a83t-de2-clk"; > > > + reg = <0x01000000 0x100000>; > > > + clocks = <&ccu CLK_BUS_DE>, > > > + <&ccu CLK_DE>; > > > + clock-names = "bus", > > > + "mod"; > > > + resets = <&ccu RST_BUS_DE>; > > > + #clock-cells = <1>; > > > + #reset-cells = <1>; > > > + assigned-clocks = <&ccu CLK_DE>; > > > + assigned-clock-parents = <&ccu CLK_PLL_DE>; > > > + assigned-clock-rates = <432000000>; > > > + }; > > > > We discussed that already a few times, but there's no reason to do > > so. If you need a downstream clock at a particular rate, call > > clk_set_rate on it, period. > > > > Whether its parent will be coming from PLL_DE or some other more > > appriopriate clock is not relevant and doesn't make any difference. > > The clock framework is not so smart to deal with these infomations: > - CLK_PLL_PERIPH should always be 600MHz > - CLK_TVE should always be 216MHz > - CLK_DE (in fact CLK_MIXER{0,1}) should be larger than 300MHz (for 4K) None of what you're doing guarantees what you state above, so I'm not really sure what your point is. > So we have to specify CLK_DE to be 432MHz, and then it will set > CLK_PLL_DE to this value, then the CLK_TVE can be set to 216MHz with > divider 2. Yes, but it works by accident. Any clock change somewhere in the same clock-tree might break whatever you have set in the DT. Hence why you want to do it within the clock framework and your driver, not here. Maxime -- Maxime Ripard, Free Electrons Embedded Linux and Kernel engineering http://free-electrons.com
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