On 05/30/2017 08:23 PM, Andy Shevchenko wrote:
> On Sun, May 28, 2017 at 9:39 PM, Hauke Mehrtens <hauke@xxxxxxxxxx> wrote:
>> From: Martin Blumenstingl <martin.blumenstingl@xxxxxxxxxxxxxx>
>>
>> Instead of hacking the configuration of the FPI bus into the arch code
>> add an own bus driver for this internal bus. The FPI bus is the main
>> bus of the SoC. This bus driver makes sure the bus is configured
>> correctly before the child drivers are getting initialized. This driver
>> will probably also be used on different SoC later.
>
>> +Optional properties:
>> +- regmap : A phandle to the RCU syscon
>
>> +- offset-endianness : Offset of the endianness configuration register
>
> Shouldn't be one of
>
> big-endian;
> little-endian;
> native-endian;
>
> ?
The offset-endianness is the offset of the endianes register in the RCU
register range which is accessed through the syscon. For the SoCs where
I checked it is the same value. I should add a documentation of big-endian.
> For what purpose that register is used?
> Is it configurable in RTL? IOW why you need to have it in DT?
>
>> + offset-endianness = <0x4c>;
>> + big-endian;
>
>> + /* RCU configuration is optional */
>> + rcu_regmap = syscon_regmap_lookup_by_phandle(np, "regmap");
>
>> + if (!IS_ERR_OR_NULL(rcu_regmap)) {
>
> _OR_NULL is suspicious. You are doing something wrong.
>
This is only needed for some SoCs, some chips do not have this register.
Should I do this based on the compatibility string?
Hauke
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