The divider of the audio PLL has an offset of 1.
Fix this in the driver.
Signed-off-by: Chen-Yu Tsai <wens@xxxxxxxx>
---
drivers/clk/sunxi-ng/ccu-sun8i-a83t.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-a83t.c b/drivers/clk/sunxi-ng/ccu-sun8i-a83t.c
index a9c5cc87d9d0..947f9f6e05d2 100644
--- a/drivers/clk/sunxi-ng/ccu-sun8i-a83t.c
+++ b/drivers/clk/sunxi-ng/ccu-sun8i-a83t.c
@@ -80,7 +80,7 @@ static struct ccu_nm pll_audio_clk = {
.enable = BIT(31),
.lock = BIT(2),
.n = _SUNXI_CCU_MULT_OFFSET_MIN_MAX(8, 8, 0, 12, 0),
- .m = _SUNXI_CCU_DIV_OFFSET(0, 6, 0),
+ .m = _SUNXI_CCU_DIV(0, 6),
.common = {
.reg = SUN8I_A83T_PLL_AUDIO_REG,
.lock_reg = CCU_SUN8I_A83T_LOCK_REG,
--
2.11.0
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