On 05/02/2017 12:55 AM, Jeremy Kerr wrote:
This change introduces a proposed layout for describing FSI busses in
the device tree. While the bus is probe-able, we'd still like a method
of describing subordinate (eg i2c) busses that are behind FSI devices.
The FSI core will be responsible for matching probed slaves & engines to
their device tree nodes, so the FSI device drivers' probe() functions
will be passed a struct device with the appropriate of_node populated
where a matching DT node is found.
RFC at this stage, so I'd welcome any feedback.
Signed-off-by: Jeremy Kerr <jk@xxxxxxxxxx>
---
+
+Full example
+------------
+
+ /* The GPIO-based FSI master node, describing the top level of the
+ * FSI bus
+ */
+ gpio-fsi {
+ compatible = "fsi-master-gpio", "fsi-master";
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ /* A FSI slave (aka. CFAM) at link 0, ID 0. */
+ cfam@0,0 {
+ reg = <0 0>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ /* FSI engine at 0xc00, using a single page. In this example,
+ * it's an I2C master controller, so subnodes describe the
+ * I2C bus.
+ */
+ i2c-controller@c00 {
+ reg = <0xc00 0x400>;
+
+ /* Engine-specific data. In this case, we're describing an
+ * I2C bus, so we're conforming to the generic I2C binding
+ */
+ compatible = "ibm,fsi-i2c";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ /* I2C endpoint device: an Atmel EEPROM */
+ eeprom@50 {
+ compatible = "atmel,24c256";
+ reg = <0x50>;
+ pagesize = <64>;
+ };
I have no problem with this as an example, but it isn't exactly how the
tree will look under the p8/p9 fsi-attached i2c master. We will instead
need a list of ports on the master. Then you could put actual devices
(eeproms, etc) under the ports if desired.
Looks like good documentation to me though. This is working well for my
I2C driver in combination with your latest FSI patches, Jeremy.
Acked-by: Eddie James <eajames@xxxxxxxxxxxxxxxxxx>
+ };
+ };
+ };
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