On Fri, Apr 7, 2017 at 2:59 PM, Andrew Jeffery <andrew@xxxxxxxx> wrote: > Each GPIO in the Aspeed GPIO controller can choose one of four input > debounce states: to disable debouncing for an input, or select from one > of three programmable debounce timer values. Each GPIO in a > four-bank-set is assigned one bit in each of two debounce configuration > registers dedicated to the set, and selects a debounce state by > configuring the two bits to select one of the four options. > > The limitation on debounce timer values is managed by mapping offsets > onto a configured timer value and keeping count of the number of users > a timer has. Timer values are configured on a first-come-first-served > basis. > > A small twist in the hardware design is that the debounce configuration > register numbering is reversed with respect to the binary representation > of the debounce timer of interest (i.e. debounce register 1 represents > bit 1, and debounce register 2 represents bit 0 of the timer numbering). > > Tested on an AST2500EVB with additional inspection under QEMU's > romulus-bmc machine. > > Signed-off-by: Andrew Jeffery <andrew@xxxxxxxx> Patch applied. Yours, Linus Walleij -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
