On Tuesday 07 January 2014 16:35:01 Arnd Bergmann wrote: > > >> +SoC specific DT Entry: > > >> + pcie0: pcie@1f2b0000 { > > >> + status = "disabled"; > > >> + device_type = "pci"; > > >> + compatible = "xgene,pcie"; > > >> + #interrupt-cells = <1>; > > >> + #size-cells = <2>; > > >> + #address-cells = >; > > >> + reg = < 0x00 0x1f2b0000 0x0 0x00010000>; > > >> + ranges = <0x02000000 0x0 0x00000000 0xe0 0x00000000 0x0 0x10000000 /* mem*/ > > > > > > > > > Also, do you support no prefetchable memory? > > > > HW has either IO or Memory regions for mapping device's memory space. > > There is no separate prefetchable memory space. > > Are you sure the memory is non-prefetchable then? I would have expected > 0x42000000 rather than 0x02000000, but I could be misremembering it. Nevermind. I just checked and you are right: if you only have one memory range, it has to be non-prefetchable. Arnd -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html