Hi Priit,
On 27 March 2017 at 04:20, Priit Laes <plaes@xxxxxxxxx> wrote:
> +static struct ccu_nkmp pll_ve_clk = {
> + .enable = BIT(31),
> + .n = _SUNXI_CCU_MULT_OFFSET(8, 5, 0),
> + .k = _SUNXI_CCU_MULT(4, 2),
> + .m = _SUNXI_CCU_DIV(0, 2),
> + .p = _SUNXI_CCU_DIV(16, 2),
> + .common = {
> + .reg = 0x018,
> + .hw.init = CLK_HW_INIT("pll-ve",
> + "hosc",
> + &ccu_nkmp_ops,
> + 0),
> + },
> +};
pll-ve is a NKMP clock in A10 but a NK clock in A20.
> +static const char *const hdmi_parents[] = { "pll-video0", "pll-video0-2x",
> + "pll-vide01", "pll-video1-2x" };
"pll-vide01" should be "pll-video1".
Regards,
Jonathan
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