Hi Bean,
On Mon, 3 Apr 2017 11:31:05 +0000
"Bean Huo (beanhuo)" <beanhuo@xxxxxxxxxx> wrote:
> Hi, Boris and Thomas
>
> >>
> >> Ok, but I recommend that 70s should be the first choice on this single
> >> solution, it doesn't need to read twice to detect its bitflips count.
> >
> >That's exactly why we need to differentiate the 2 chips.
>
> Sorry for later this response.
> Below is the pseudo codes about how to differentiate these 2 series parallel
> NAND with on-die ECC:
>
> if (NAND == SLC ) { // on-die ECC only exists in SLC
> //check device ID byte 4
> if ((ID.byte4 & 0x02) == 0x02) {// internal ECC level ==10b
So here the MT29F1G08ABADAWP datasheet says 0x2 <=> 4bit/512bytes ECC.
> if (ID.byte4 & 0x80) {//on-Die ECC enabled
Did you read my last reply?
Thomas discovered that ID[4].bit7 is actually reflecting the ECC engine
state (1 if the engine is enabled, 0 if it's disabled), not whether the
NAND supports on-die ECC or not, so no this test is not reliable.
> if (ONFI.byte112 == 4)
> 60s SLC NAND with on-die ECC
> else if (ONFI.byte112 == 8)
> 70s SLC NAND with on-die ECC
This is completely fucked up! Now the ONFI param page says the NAND
requires 8bits/512bytes, while the ID bytes advertised an on-die ECC
providing 4bits/512bytes correctability.
So either your algorithm is wrong, or the ID and ONFI param page are
contracting (not sure what solution I'd prefer...).
> else
> Doesn't support on-die ECC
Sorry to say that, but I find it worrisome that even someone from Micron
is not able to get it right.
I think we'll stick to the model name to detect whether on-die ECC is
supported.
Regards,
Boris
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo@xxxxxxxxxxxxxxx
More majordomo info at http://vger.kernel.org/majordomo-info.html
