On Fri, Apr 07, 2017 at 03:04:01PM +0530, Laxman Dewangan wrote: > In some of NVIDIA Tegra's platform, PWM controller is used to > control the PWM controlled regulators. PWM signal is connected to > the VID pin of the regulator where duty cycle of PWM signal decide > the voltage level of the regulator output. > > When system enters suspend, some PWM client/slave regulator devices > require the PWM output to be tristated. > > Add DT binding details to provide the pin configuration state > from PWM and pinctrl DT node in suspend and active state of > the system. > > Signed-off-by: Laxman Dewangan <ldewangan@xxxxxxxxxx> > > --- > Changes from v1: > - Use standard pinctrl names for sleep and active state. > > Changes from V2: > - Fix the commit message and details > --- > .../devicetree/bindings/pwm/nvidia,tegra20-pwm.txt | 45 ++++++++++++++++++++++ > 1 file changed, 45 insertions(+) Acked-by: Rob Herring <robh@xxxxxxxxxx> -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
