This series adds support for IDT VersaClock 5P49V5935 programmable clock generator to the existing clk-versaclock5 driver. Patches were verified on Avnet UltraZed-EG board with IO Carrier Card. Changes in V2: - Introduce vc5_chip_info structure describing chip features - Set vc5_chip_info for the supported chips using clk_vc5_of_match[].data - Add 5P49V5935 support using vc5_chip_info approach - Fix idx comparison in vc5_of_clk_get ('>' to '>=') Changes in V3: - Change type of clk_fod_cnt and clk_out_cnt to unsigned int - Add missed 'const' to vc5_chip_info instance declaration - Use of_device_get_match_data() to initialize vc5_chip_info on probe Alexey Firago (3): clk: vc5: Add structure to describe particular chip features clk: vc5: Add bindings for IDT VersaClock 5P49V5935 clk: vc5: Add support for IDT VersaClock 5P49V5935 .../devicetree/bindings/clock/idt,versaclock5.txt | 16 ++++- drivers/clk/clk-versaclock5.c | 76 +++++++++++++++++----- 2 files changed, 71 insertions(+), 21 deletions(-) -- 2.7.4 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html