On Wed, Apr 5, 2017 at 3:28 PM, Maxime Ripard <maxime.ripard@xxxxxxxxxxxxxxxxxx> wrote: > On Wed, Apr 05, 2017 at 02:20:31PM +0800, Chen-Yu Tsai wrote: >> On Wed, Apr 5, 2017 at 2:11 PM, Maxime Ripard >> <maxime.ripard@xxxxxxxxxxxxxxxxxx> wrote: >> > On Wed, Apr 05, 2017 at 11:51:45AM +0800, Chen-Yu Tsai wrote: >> >> On Wed, Apr 5, 2017 at 2:01 AM, Icenowy Zheng <icenowy@xxxxxxx> wrote: >> >> > Allwinner A64 SoC features a NMI controller, which is usually connected >> >> > to the AXP PMIC. >> >> > >> >> > Add support for it. >> >> > >> >> > Signed-off-by: Icenowy Zheng <icenowy@xxxxxxx> >> >> >> >> This might not be the best representation of the R_INTC block. Though >> >> we'd need to change it for all SoCs if we want to be accurate. For now, >> > >> > What do you think would be a good representation? >> >> My gut feeling is that this is the old INTC from sun4/5i. > > Ah, that would make sense. > >> It's supposed to be the interrupt controller for the embedded low >> power core. I've not done a thorough comparison though. > > Do we have some documentation / code for this one? I can't remember where or if I saw any. If Allwinner ever released any source code for the OpenRISC core we could actually verify it. However the base address of this block, in addition to the register offsets found in the driver for "allwinner,sun6i-a31-sc-nmi" do match up with the sun4i irqchip. The question is if any of the other interrupt lines are hooked up, and if yes, to what. A possibility would be that it has all the interrupt lines in the SoC also hooked up, at the same numbers as the GIC (minus 32). It would feed both the GIC and CPUS. This is just an educated guess though. Regards ChenYu -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
