Hi Boris, 2017-03-30 23:02 GMT+09:00 Boris Brezillon <boris.brezillon@xxxxxxxxxxxxxxxxxx>: > On Thu, 30 Mar 2017 15:46:00 +0900 > Masahiro Yamada <yamada.masahiro@xxxxxxxxxxxxx> wrote: > >> Historically, this driver tried to choose as big ECC strength as >> possible, but it would be reasonable to allow DT to set a particular >> ECC strength with "nand-ecc-strength" property. This is useful >> when a particular ECC setting is hard-coded by firmware (or hard- >> wired by boot ROM). >> >> If no ECC strength is specified in DT, "nand-ecc-maximize" is implied >> since this was the original behavior. > > You said there is currently no DT users, Right. No DT users ever in upstream. > so how about changing the > "fallback to ECC maximization" behavior for DT users, and instead of > maximizing the ECC strength take the NAND requirements into account > (chip->ecc_strength_ds). This is difficult to judge in some cases. As I said before, 4/512 and 8/1024 are not equivalent. If chip's requirement chip->ecc_step_ds matches to the ecc->size supported by the controller, this is easy. If a chip requests 1024B, then the controller can only support 512B chunk (or vice versa), it is difficult to simply compare ecc strength. Is it a bad thing if we use too strong ECC strength? The disadvantage I see is we will have less OOB-free bytes, but this will not be fatal, I guess. -- Best Regards Masahiro Yamada -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
