On Fri, 24 Mar 2017 10:18:29 -0500 Rob Herring <robh@xxxxxxxxxx> wrote: > On Sat, Mar 18, 2017 at 04:43:01PM +0100, Ralph Sennhauser wrote: > > From: Andrew Lunn <andrew@xxxxxxx> > > > > Armada 370/XP devices can 'blink' gpio lines with a configurable on > > and off period. This can be modelled as a PWM. > > > > However, there are only two sets of PWM configuration registers for > > all the gpio lines. This driver simply allows a single gpio line per > > gpio chip of 32 lines to be used as a PWM. Attempts to use more > > return EBUSY. > > > > Due to the interleaving of registers it is not simple to separate > > the PWM driver from the gpio driver. Thus the gpio driver has been > > extended with a PWM driver. > > > > Signed-off-by: Andrew Lunn <andrew@xxxxxxx> > > URL: https://patchwork.ozlabs.org/patch/427287/ > > URL: https://patchwork.ozlabs.org/patch/427295/ > > [Ralph Sennhauser: > > * port forward > > * merge pwm portion into gpio-mvebu.c > > * merge documentation patch > > * update MAINTAINERS] > > Signed-off-by: Ralph Sennhauser <ralph.sennhauser@xxxxxxxxx> > > --- > > .../devicetree/bindings/gpio/gpio-mvebu.txt | 31 +++ > > MAINTAINERS | 2 + > > drivers/gpio/gpio-mvebu.c | 291 > > +++++++++++++++++++-- 3 files changed, 307 insertions(+), 17 > > deletions(-) > > > > diff --git a/Documentation/devicetree/bindings/gpio/gpio-mvebu.txt > > b/Documentation/devicetree/bindings/gpio/gpio-mvebu.txt index > > a6f3bec..86932e3 100644 --- > > a/Documentation/devicetree/bindings/gpio/gpio-mvebu.txt +++ > > b/Documentation/devicetree/bindings/gpio/gpio-mvebu.txt @@ -38,6 > > +38,23 @@ Required properties: > > - #gpio-cells: Should be two. The first cell is the pin number. The > > second cell is reserved for flags, unused at the moment. > > > > +Optional properties: > > + > > +In order to use the gpio lines in PWM mode, some additional > > optional +properties are required. Only Armada 370 and XP support > > these properties. + > > +- reg: an additional register set is needed, for the GPIO Blink > > + Counter on/off registers. > > + > > +- reg-names: Must contain an entry "pwm" corresponding to the > > + additional register range needed for pwm operation. > > + > > +- #pwm-cells: Should be two. The first cell is the pin number. > > The > > s/pin number/gpio line/ ? Better indeed. > > > + second cell is reserved for flags and should be set to 0, so it > > has a > > + known value. It then becomes possible to use it in the future. > > + > > +- clocks: Must be a phandle to the clock for the gpio controller. > > + > > Example: > > > > gpio0: gpio@d0018100 { > > @@ -51,3 +68,17 @@ Example: > > #interrupt-cells = <2>; > > interrupts = <16>, <17>, <18>, <19>; > > }; > > + > > + gpio1: gpio@18140 { > > + compatible = "marvell,orion-gpio"; > > If only 370 and XP support this, I'd expect a compatible string for > one of them here. Commit 5f79c651e81e ("arm: mvebu: use global interrupts for GPIOs on Armada XP") changes it from "marvell,armadaxp-gpio". The commit message says for 3.8 basically leaving it open for a "fix" later. Adding Thomas Petazzoni as the author. Thomas, would you happen to know if this is still how it's supposed to be for now? Thanks Ralph > > > + reg = <0x18140 0x40>, <0x181c8 0x08>; > > + reg-names = "gpio", "pwm"; > > + ngpios = <17>; > > + gpio-controller; > > + #gpio-cells = <2>; > > + #pwm-cells = <2>; > > + interrupt-controller; > > + #interrupt-cells = <2>; > > + interrupts = <87>, <88>, <89>; > > + clocks = <&coreclk 0>; > > + }; -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
