On Fri, Mar 24, 2017 at 09:59:08AM -0500, Rob Herring wrote: > On Fri, Mar 17, 2017 at 01:11:12PM -0700, Moritz Fischer wrote: > > This adds the binding documentation for the Xilinx LogiCORE PR > > Decoupler soft core. > > > > Signed-off-by: Moritz Fischer <mdf@xxxxxxxxxx> > > Cc: Michal Simek <michal.simek@xxxxxxxxxx> > > Cc: Sören Brinkmann <soren.brinkmann@xxxxxxxxxx> > > Cc: linux-kernel@xxxxxxxxxxxxxxx > > Cc: devicetree@xxxxxxxxxxxxxxx > > --- > > > > Changes from v2: > > - Added refence to generic fpga-region bindings > > - Fixed up reg property in example > > - Added fallback to "xlnx,pr-decoupler" without version > > > > Changes from v1: > > - Added clock names & clock to example > > - Merged some of the description from Michal's version > > > > --- > > .../bindings/fpga/xilinx-pr-decoupler.txt | 35 ++++++++++++++++++++++ > > 1 file changed, 35 insertions(+) > > create mode 100644 Documentation/devicetree/bindings/fpga/xilinx-pr-decoupler.txt > > > > diff --git a/Documentation/devicetree/bindings/fpga/xilinx-pr-decoupler.txt b/Documentation/devicetree/bindings/fpga/xilinx-pr-decoupler.txt > > new file mode 100644 > > index 0000000..16141bd > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/fpga/xilinx-pr-decoupler.txt > > @@ -0,0 +1,35 @@ > > +Xilinx LogiCORE Partial Reconfig Decoupler Softcore > > + > > +The Xilinx LogiCORE Partial Reconfig Decoupler manages one or more > > +decouplers / fpga bridges. > > +The controller can decouple/disable the bridges which prevents signal > > +changes from passing through the bridge. The controller can also > > +couple / enable the bridges which allows traffic to pass through the > > +bridge normally. > > + > > +The Driver supports only MMIO handling. A PR region can have multiple > > +PR Decouples which can bhe handled independently or chaines via decouple/ > > s/chaines/chains/ Fixed in v4. > > +decouple_status signals. > > + > > +Required properties: > > +- compatible : Should contain "xlnx,pr-decoupler-1.00" > > +- regs : base address and size for decoupler module > > +- clocks : input clock to IP > > +- clock-names : should contain "aclk" > > + > > +Optional properties: > > +- bridge-enable : 0 if driver should disable bridge at startup > > + 1 if driver should enable bridge at startup > > + Default is to leave bridge in current state. > > This is common and should move into a common doc. Maybe fpga-region.txt > works? Ok will add patch for that to v5 series. Thanks for your feedback, Moritz -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
