On Tue, Mar 21, 2017 at 4:02 PM, <matthew.gerlach@xxxxxxxxxxxxxxx> wrote: > From: Matthew Gerlach <matthew.gerlach@xxxxxxxxxxxxxxx> > > Adding the core functions necessary for a fpga-mgr driver > for the Altera Partial IP component. It is intended for > these functions to be used by the various bus implementations > like the platform bus or the PCIe bus. > > Signed-off-by: Matthew Gerlach <matthew.gerlach@xxxxxxxxxxxxxxx> Acked-by: Alan Tull <atull@xxxxxxxxxx> > --- > v6: > Suggestions from Anatolij Gustschin <agust@xxxxxxx> > s/pr_err/dev_err/g > Change for loop to do/while to handle config_complete_timeout_us == 0 > move altera-pr-ip-core.h to include/linux/fpga > v5: > Fix comment as suggested by Rob Herring <robh@xxxxxxxxxx> > v4: > v3 patch set mistakenly sent out labeled as v4 > v3: > s/alt_pr_probe/alt_pr_register/ > s/alt_pr_remove/alt_pr_unregister/ > -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
