On Tue, Mar 7, 2017 at 6:34 AM, Icenowy Zheng <icenowy@xxxxxxxx> wrote: > Allwinner H3/V3s/A64 SoCs have a special USB PHY0 that can route to two > controllers: one is MUSB and the other is a EHCI/OHCI pair. > > When it's routed to EHCI/OHCI pair, it will needs a "pmu0" regs to > tweak, like other EHCI/OHCI pairs in Allwinner SoCs. > > Add this to the binding of USB PHYs on Allwinner H3/V3s/A64. > > Signed-off-by: Icenowy Zheng <icenowy@xxxxxxxx> Acked-by: Chen-Yu Tsai <wens@xxxxxxxx> -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
