On Tue, 2017-02-28 at 14:01 -0300, Emilio López wrote:
> Hi,
>
> I spotted a couple of things here on a quick look, see below
>
> El 27/02/17 a las 18:09, Priit Laes escribió:
> > Convert sun7i-a20.dtsi to new CCU driver.
> >
> > > > Signed-off-by: Priit Laes <plaes@xxxxxxxxx>
> > ---
> > arch/arm/boot/dts/sun7i-a20.dtsi | 719 +++++----------------------------------
> > 1 file changed, 86 insertions(+), 633 deletions(-)
> >
> > diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
> > index 04c9977..6f80cb8 100644
> > --- a/arch/arm/boot/dts/sun7i-a20.dtsi
> > +++ b/arch/arm/boot/dts/sun7i-a20.dtsi
> > @@ -47,7 +47,8 @@
> > #include <dt-bindings/interrupt-controller/arm-gic.h>
> > #include <dt-bindings/thermal/thermal.h>
> >
> > -#include <dt-bindings/clock/sun4i-a10-pll2.h>
> > +#include <dt-bindings/clock/sun7i-ccu.h>
> > +#include <dt-bindings/reset/sun7i-ccu.h>
> > #include <dt-bindings/dma/sun4i-a10.h>
> > #include <dt-bindings/pinctrl/sun4i-a10.h>
> >
> > @@ -67,19 +68,19 @@
> > > > compatible = "allwinner,simple-framebuffer",
> > > > "simple-framebuffer";
> > > > allwinner,pipeline = "de_be0-lcd0-hdmi";
> > > > - clocks = <&ahb_gates 36>, <&ahb_gates 43>,
> > > > - <&ahb_gates 44>, <&de_be0_clk>,
> > > > - <&tcon0_ch1_clk>, <&dram_gates 26>;
> > > > + clocks = <&ccu CLK_AHB_LCD0>, <&ccu CLK_AHB_HDMI1>,
> > > > + <&ccu CLK_AHB_DE_BE0>, <&ccu CLK_DE_BE0>,
> > > > + <&ccu CLK_TCON0_CH1>, <&ccu CLK_DRAM_DE_BE0>;
> > > > status = "disabled";
> > > > };
> >
> > > > - framebuffer@1 {
> > + framebuffer@0 {
>
> This looks like an unrelated change
Yup, that 's leftover from changes made during initial debugging. Will
fix in v2.
>
> > @@ -184,21 +185,11 @@
> >
> > > > > > osc24M: clk@01c20050 {
> > > > #clock-cells = <0>;
> > > > - compatible = "allwinner,sun4i-a10-osc-clk";
> > > > - reg = <0x01c20050 0x4>;
> > > > + compatible = "fixed-clock";
> > > > clock-frequency = <24000000>;
> > > > clock-output-names = "osc24M";
> > };
>
> allwinner,sun4i-a10-osc-clk implements a gate apart from a fixed clock,
> is the feature loss intended?
This is how most of the existing drivers handle it (A13, A31, A33) so I
didn't want to do anything fancy..
Besides, the code for clock actually configures gate:
static SUNXI_CCU_GATE(hosc_clk, "hosc", "osc24M", 0x050, BIT(0), 0);
Päikest,
Priit
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