On Mon, Feb 20, 2017 at 04:02:22PM +0800, Chris Zhong wrote:
> Set the lanes bps to 1 / 0.9 times of pclk, the margin is not enough
> for some panel, it will cause the screen display is not normal, so
> increases the badnwidth to 1 / 0.8.
>
> Signed-off-by: Chris Zhong <zyw@xxxxxxxxxxxxxx>
Reviewed-by: Sean Paul <seanpaul@xxxxxxxxxxxx>
> ---
>
> Changes in v6: None
> Changes in v5: None
> Changes in v4: None
> Changes in v3: None
>
> drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
> index c2d7674..a653384 100644
> --- a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
> +++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
> @@ -532,8 +532,8 @@ static int dw_mipi_dsi_get_lane_bps(struct dw_mipi_dsi *dsi,
>
> mpclk = DIV_ROUND_UP(mode->clock, MSEC_PER_SEC);
> if (mpclk) {
> - /* take 1 / 0.9, since mbps must big than bandwidth of RGB */
> - tmp = mpclk * (bpp / dsi->lanes) * 10 / 9;
> + /* take 1 / 0.8, since mbps must big than bandwidth of RGB */
> + tmp = mpclk * (bpp / dsi->lanes) * 10 / 8;
> if (tmp < max_mbps)
> target_mbps = tmp;
> else
> --
> 2.6.3
>
> _______________________________________________
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--
Sean Paul, Software Engineer, Google / Chromium OS
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