Hi Steve, On Tue, Jan 31, 2017 at 05:02:40PM -0800, Steve Longerbeam wrote: > But this also puts a requirement on MIPI sensors that s_power(ON) > should only place the D_PHY in LP-11, and _not_ start the clock lane. > But perhaps that is correct behavior anyway. If the CSI2 DPHY is held in reset state, it shouldn't matter what the sensor does. In the case of IMX219, it needs a full setup of the device, including enabling it to stream (so it starts the clock lane etc) in order to get it into LP-11 state. Merely disabling the XCLR signal leaves the lanes grounded. I do seem to remember reading in one of the MIPI specs that this is rather expected behaviour, though I can't point at a paragraph this late in the night. So, the only way to satisfy these requirements is this order: - assert PHY reset signals (so blocking any activity on the CSI lanes) - initialise the sensor (including allowing it to start streaming and then stopping the stream - at that point, the lanes will be in LP-11.) - deassert the resets as per the iMX6 documentation and follow the remaining procedure. I'll look at your other points tomorrow. Thanks. -- RMK's Patch system: http://www.armlinux.org.uk/developer/patches/ FTTC broadband for 0.8mile line: currently at 9.6Mbps down 400kbps up according to speedtest.net. -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
