On Sat, Jan 28, 2017 at 3:56 PM, Linus Walleij <linus.walleij@xxxxxxxxxx> wrote:
> On Mon, Jan 23, 2017 at 9:21 PM, Rob Herring <robh@xxxxxxxxxx> wrote:
>> On Sun, Jan 22, 2017 at 01:22:19PM +0100, Linus Walleij wrote:
>>> This adds the top level SoC bindings for Cortina systems Gemini
>>> platforms.
> (...)
>>> +- intcon: the root node must have an interrupt controller node pointing to
>>
>> intcon is just a source label and not meaningful for the binding.
>
> OK
>
>>> +Example:
>>> +
>>> +/ {
>>> + interrupt-parent = <&intcon>;
>>> +
>>> + syscon: syscon@40000000 {
>>
>> This chip has no internal bus? Put all these nodes under a bus.
>
> Are you thinking something of the form:
>
> soc: soc {
> #address-cells = <1>;
> #size-cells = <1>;
> ranges;
> compatible = "simple-bus";
>
> syscon: syscon@40000000 {
>
> (...)
>
> ?
Yes.
Rob
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