The TI AEMIF driver registers are used to setup timings for each chip
select. The same registers range is used to setup NAND settings.
The AEMIF and NAND drivers not use the same registers in this range.
In case with TI AEMIF driver, the memory address range is requested
already by AEMIF, so we cannot request it twice, just ioremap.
Acked-by: Santosh Shilimkar <santosh.shilimkar@xxxxxx>
Reviewed-by: Grygorii Strashko <grygorii.strashko@xxxxxx>
Reviewed-by: Taras Kondratiuk <taras@xxxxxx>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@xxxxxx>
---
drivers/mtd/nand/davinci_nand.c | 14 +++++++++++---
1 file changed, 11 insertions(+), 3 deletions(-)
diff --git a/drivers/mtd/nand/davinci_nand.c b/drivers/mtd/nand/davinci_nand.c
index 8a61a40..0104d26 100644
--- a/drivers/mtd/nand/davinci_nand.c
+++ b/drivers/mtd/nand/davinci_nand.c
@@ -637,9 +637,17 @@ static int nand_davinci_probe(struct platform_device *pdev)
if (IS_ERR(vaddr))
return PTR_ERR(vaddr);
- base = devm_ioremap_resource(&pdev->dev, res2);
- if (IS_ERR(base))
- return PTR_ERR(base);
+ /*
+ * This registers range is used to setup NAND settings. In case with
+ * TI AEMIF driver, the same memory address range is requested already
+ * by AEMIF, so we cannot request it twice, just ioremap.
+ * The AEMIF and NAND drivers not use the same registers in this range.
+ */
+ base = devm_ioremap(&pdev->dev, res2->start, resource_size(res2));
+ if (!base) {
+ dev_err(&pdev->dev, "ioremap failed for resource %pR\n", res2);
+ return -EADDRNOTAVAIL;
+ }
info->dev = &pdev->dev;
info->base = base;
--
1.7.9.5
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