On 01/27/2017 05:13 AM, Stephen Boyd wrote:
On 01/24, Vivek Gautam wrote:Below is one binding that works for me. -------------------- phy@34000 { compatible = "qcom,msm8996-qmp-pcie-phy"; reg = <0x034000 0x488>; #clock-cells = <1>; #address-cells = <1>; #size-cells = <1>; ranges; clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, <&gcc GCC_PCIE_PHY_CFG_AHB_CLK>, <&gcc GCC_PCIE_CLKREF_CLK>; clock-names = "aux", "cfg_ahb", "ref"; vdda-phy-supply = <&pm8994_l28>; vdda-pll-supply = <&pm8994_l12>; resets = <&gcc GCC_PCIE_PHY_BCR>, <&gcc GCC_PCIE_PHY_COM_BCR>, <&gcc GCC_PCIE_PHY_COM_NOCSR_BCR>; reset-names = "phy", "common", "cfg"; pciephy_p0: port@0 {The unit address '@0' should be replaced with something from the reg properties.
Sure, will take care of this.
Also 'port' and 'ports' are almost keywords in DT now with the graph binding so we need to be careful when using them.
From "./Documentation/devicetree/bindings/graph.txt" - "The device tree graph bindings described herein abstract more complex devices that can have multiple specifiable ports, each of which can be linked to one or more ports of other devices." So, this means we use 'port', 'ports' and 'endpoint' for devices whose one or more ports is connected to other device's one or more ports. I can use 'lane' for the node name here.
reg = <0x035000 0x130>, <0x035200 0x200>, <0x035400 0x1dc>; #phy-cells = <0>; clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; clock-names = "pipe0"; resets = <&gcc GCC_PCIE_0_PHY_BCR>; reset-names = "lane0"; }; pciephy_p1: port@1 { reg = <0x036000 0x130>, <0x036200 0x200>, <0x036400 0x1dc>; #phy-cells = <0>; clocks = <&gcc GCC_PCIE_1_PIPE_CLK>; clock-names = "pipe1"; resets = <&gcc GCC_PCIE_1_PHY_BCR>; reset-names = "lane1"; }; pciephy_p2: port@2 { reg = <0x037000 0x130>, <0x037200 0x200>, <0x037400 0x1dc>; #phy-cells = <0>; clocks = <&gcc GCC_PCIE_2_PIPE_CLK>; clock-names = "pipe2"; resets = <&gcc GCC_PCIE_2_PHY_BCR>; reset-names = "lane2"; }; }; -------------------- let me know if this looks okay.What's the plan for non-pcie qmp phy binding? In that case we don't have ports, so it gets folded into one node?
The non-pcie qmp phys still have one lane, that provides tx/rx. I am of the opinion that we don't have two different ways to create phys in the driver, and keep one port/lane for such phys in dt. Regards Vivek -- The Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
