Stephen Boyd <sboyd@xxxxxxxxxxxxxx> writes: > On 01/19, Martin Blumenstingl wrote: >> The HHI_SAR_CLK_CNTL contains three SAR ADC specific clocks: >> - a mux clock to choose between different ADC reference clocks (this is >> 2-bit wide, but the datasheet only lists the parents for the first >> bit) >> - a divider for the input/reference clock >> - a gate which enables the ADC clock >> >> Additionally this exposes the ADC core clock (CLKID_SAR_ADC) and >> CLKID_SANA (which seems to enable the analog inputs, but unfortunately >> there is no documentation for this - we just mimic what the vendor >> driver does). >> >> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@xxxxxxxxxxxxxx> >> Tested-by: Neil Armstrong <narmstrong@xxxxxxxxxxxx> >> --- > > Acked-by: Stephen Boyd <sboyd@xxxxxxxxxxxxxx> > > This should go through arm-soc along with the other patch to dts. Applied to v4.11/dt64 of the amlogic tree. Kevin -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
