Hi, Bryan O'Donoghue <pure.logic@xxxxxxxxxxxxxxxxx> writes: > On 19/01/17 22:49, John Youn wrote: > >> So it is valid to have say, DWC_USB3_NUM_EPS=8 and >> DWC_USB3_NUM_IN_EPS=8. Even though it is not possible to use all 8 EPs >> as IN since you need at least one of them to be a control OUT. So you >> could have a configuration of EP0 IN and OUT plus 6 IN EPs (total 1 >> OUT, 7 IN). Or EP0 IN and OUT plus any other combination of IN/OUT for >> the remaining 6 EPs. >> >> With the above in mind, you can probably just redo the endpoint number >> logic in dwc3 to handle all cases without any quirks at all. > > I thought of that. > >> If it is disabled, it will fix the physical and logical EP number and >> direction of the available EPs to meet timings for FPGA designs. This >> shouldn't be used in final designs for ASICS but we don't know for >> sure whether it has made it to any final designs or not. >> >> And unfortunately, whether this is set or not is not visible to the >> software so it will require a quirk. > > but arrived at this conclusion because I couldn't think of a reasonable > guess value for IN/OUT endpoint numbers that would work if > DWC_USB3_NUM_EPS == DWC_USB3_NUM_IN_EPS Well, we can, for now at least, take the simple approach of half IN, half OUT. If DWC3_USB3_NUM_EPS is odd, then OUT should take the extra endpoint. If anybody complains, we can fix it later ;-) -- balbi
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