Hi Rob
Thank you for your feedback
> > SoC.0 Codec0
> > SoC.1 <-> Card <-> Codec1
> > SoC.2 Codec2
(snip)
> The card should only have the entry (or exit) points of the graph.
> That may not even need to be graph nodes. It could just be a list of
> CPU DAI phandles (which then have graph nodes).
>
> Look at the display side use of OF graph. We have display subsystem
> nodes (like a card) with a poorly named ports property (nothing to do
> with OF graph) listing display channels. Each phandle there is the
> entry point to the graph and is typically the front end display
> controller (perhaps a CSC and scaling unit). The graph then goes to a
> backend controller (for display timing), then to interface PHY
> (DSI/HDMI), then possibly and external bridge chip, then to a
> connector or panel node. That's a complex example. In simple cases, we
> just have a display controller connected to a panel.
If my understanding here was correct, do you mean like this ?
sound_dai0 {
ports {
port { /* Card.0 */ }
port { /* SoC.0 */ }
port { /* Codec0 */ }
};
};
sound_dai1 {
ports {
port { /* Card.1 */ }
port { /* SoC.1 */ }
port { /* Codec1 */ }
};
};
sound_dai2 {
ports {
port { /* Card.2 */ }
port { /* SoC.2 */ }
port { /* Codec2 */ }
};
};
card {
ports {
port { /* sound_dai0 */ }
port { /* sound_dai1 */ }
port { /* sound_dai2 */ }
};
};
Or this ?
sound_dai0 {
ports {
port { /* SoC.0 */ }
port { /* Codec0 */ }
};
};
sound_dai1 {
ports {
port { /* SoC.1 */ }
port { /* Codec1 */ }
};
};
sound_dai2 {
ports {
port { /* SoC.2 */ }
port { /* Codec2 */ }
};
};
card {
dais = <&sound_dai0
&sound_dai1
&sound_dai2>;
};
Best regards
---
Kuninori Morimoto
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