GPIO01_IO05 is controlled by the LPSR iomux controller, so attach the corresponding pin to this controller. Signed-off-by: Sascha Hauer <s.hauer@xxxxxxxxxxxxxx> --- arch/arm/boot/dts/imx7d-cl-som-imx7.dts | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) diff --git a/arch/arm/boot/dts/imx7d-cl-som-imx7.dts b/arch/arm/boot/dts/imx7d-cl-som-imx7.dts index 58b09bf1ba2d..1135bc99b3e7 100644 --- a/arch/arm/boot/dts/imx7d-cl-som-imx7.dts +++ b/arch/arm/boot/dts/imx7d-cl-som-imx7.dts @@ -261,12 +261,6 @@ >; }; - pinctrl_usbotg1: usbotg1grp { - fsl,pins = < - MX7D_PAD_GPIO1_IO05__GPIO1_IO5 0x14 /* OTG PWREN */ - >; - }; - pinctrl_usdhc3: usdhc3grp { fsl,pins = < MX7D_PAD_SD3_CMD__SD3_CMD 0x59 @@ -283,3 +277,11 @@ >; }; }; + +&iomuxc_lpsr { + pinctrl_usbotg1: usbotg1grp { + fsl,pins = < + MX7D_PAD_GPIO1_IO05__GPIO1_IO5 0x14 /* OTG PWREN */ + >; + }; +}; \ No newline at end of file -- 2.11.0 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html