On 13/01/2017 03:15, Wolfram Sang wrote:
On Mon, Jan 09, 2017 at 05:02:54PM +0800, Phil Reid wrote:
Various muxes can aggregate multiple interrupts from each i2c bus.
All of the muxes with interrupt support combine the active low irq lines
using an internal 'and' function and generate a combined active low
output. The muxes do provide the ability to read a control register to
determine which irq is active. By making the mux an irq controller isr
latency can potentially be reduced by reading the status register and
then only calling the registered isr on that bus segment.
As there is no irq masking on the mux irq are disabled until irq_unmask is
called at least once.
Signed-off-by: Phil Reid <preid@xxxxxxxxxxxxxxxxx>
Is the ack from Peda here forgotten or still missing?
@peda: Once you are happy, do you want to take these patches via your
shiny new mux-tree or do you prefer if I pick them?
G'day Wolfram,
I think he was hoping someone else would have a look at it based on this
feedback.
On 2017-01-04 15:13, Peter Rosin wrote:
Irqs are not my strong point, I would prefer if someone else also had
a look. And there are some comments below...
--
Regards
Phil Reid
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