Hi,
On Thu, Dec 29, 2016 at 6:17 AM, Krzysztof Kozlowski <krzk@xxxxxxxxxx> wrote:
> On Thu, Dec 15, 2016 at 04:54:30PM -0800, Doug Anderson wrote:
>> > Index: b/arch/arm/boot/dts/exynos5800.dtsi
>> > ===================================================================
>> > --- a/arch/arm/boot/dts/exynos5800.dtsi 2016-12-15 12:43:54.365955950 +0100
>> > +++ b/arch/arm/boot/dts/exynos5800.dtsi 2016-12-15 12:43:54.361955949 +0100
>> > @@ -24,6 +24,16 @@
>> > };
>> >
>> > &cluster_a15_opp_table {
>> > + opp@2000000000 {
>> > + opp-hz = /bits/ 64 <2000000000>;
>> > + opp-microvolt = <1250000>;
>> > + clock-latency-ns = <140000>;
>> > + };
>> > + opp@1900000000 {
>> > + opp-hz = /bits/ 64 <1900000000>;
>> > + opp-microvolt = <1250000>;
>> > + clock-latency-ns = <140000>;
>> > + };
>>
>> I don't think the voltages you listed are high enough for all peach pi
>> boards for A15 at 1.9 GHz and 2.0 GHz, at least based on the research
>> I did. See my response to v1.
>
> I wanted to apply this but saw this remaining issue. Javier tested it
> on Peach Pi so is this concern still valid?
I'm not sure. It's been years since I did anything with exynos, so I
won't stand in the way if everyone else agrees that this patch is
good, but I will point out that testing on a single Peach Pi board is
not really enough given the massive difference in voltage needed
between the highest ASV group and the lowest (a whopping 112.5 mV from
looking in the Chrome OS source tree).
-Doug
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