On 01/04/2017 03:05 AM, Rob Herring wrote:
> On Wed, Dec 28, 2016 at 07:34:52PM +0900, Jaehoon Chung wrote:
>> Adds the exynos-pcie-phy binding for Exynos PCIe PHY.
>> This is for using generic PHY framework.
>>
>> Signed-off-by: Jaehoon Chung <jh80.chung@xxxxxxxxxxx>
>> ---
>> .../devicetree/bindings/phy/samsung-phy.txt | 23 ++++++++++++++++++++++
>> 1 file changed, 23 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/phy/samsung-phy.txt b/Documentation/devicetree/bindings/phy/samsung-phy.txt
>> index 9872ba8..1cbc15f 100644
>> --- a/Documentation/devicetree/bindings/phy/samsung-phy.txt
>> +++ b/Documentation/devicetree/bindings/phy/samsung-phy.txt
>> @@ -191,3 +191,26 @@ Example:
>> usbdrdphy0 = &usb3_phy0;
>> usbdrdphy1 = &usb3_phy1;
>> };
>> +
>> +Samsung Exynos SoC series PCIe PHY controller
>> +--------------------------------------------------
>> +Required properties:
>> +- compatible : Should be set to "samsung,exynos5440-pcie-phy"
>> +- #phy-cells : Must be zero
>> +- reg : a register used by phy driver.
>> +
>> +Required properies for child node:
>> +- reg : a block register used by phy driver.
>
> There's no need for this. Either just make the length 0x1040 or add a
> 2nd address to the parent reg prop.
Will use the 2nd address to the parent reg prop.
Because there are two pcie-phy for Exynos5440.
one block register is started from 0x271000, the other is started from 0x271040.
Best Regards,
Jaehoon Chung
>
>> +
>> +Example:
>> + pcie_phy0: pcie-phy@270000 {
>> + #phy-cells = <0>;
>> + compatible = "samsung,exynos5440-pcie-phy";
>> + reg = <0x270000 0x1000>;
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> + ranges;
>> + block@271000 {
>> + reg = <0x271000 0x40>;
>> + };
>> + };
>> --
>> 2.10.2
>>
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