On 12/20, Vivek Gautam wrote:
> PHY transceiver driver for QUSB2 phy controller that provides
> HighSpeed functionality for DWC3 controller present on
> Qualcomm chipsets.
>
> Signed-off-by: Vivek Gautam <vivek.gautam@xxxxxxxxxxxxxx>
One comment below, but otherwise
Reviewed-by: Stephen Boyd <sboyd@xxxxxxxxxxxxxx>
> +static void qusb2_phy_set_tune2_param(struct qusb2_phy *qphy)
> +{
> + struct device *dev = &qphy->phy->dev;
> + u8 *val;
> +
> + /*
> + * Read efuse register having TUNE2 parameter's high nibble.
> + * If efuse register shows value as 0x0, or if we fail to find
> + * a valid efuse register settings, then use default value
> + * as 0xB for high nibble that we have already set while
> + * configuring phy.
> + */
> + val = nvmem_cell_read(qphy->cell, NULL);
> + if (IS_ERR(val) || !val[0]) {
> + dev_dbg(dev, "failed to read a valid hs-tx trim value, %ld\n",
> + PTR_ERR(val));
If val is 0 PTR_ERR(0) will be junk? I guess that's ok for debug
print.
> + return;
> + }
> +
> + /* Fused TUNE2 value is the higher nibble only */
> + qusb2_setbits(qphy->base + QUSB2PHY_PORT_TUNE2, val[0] << 0x4);
> +}
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