On Tue, Dec 20, 2016 at 05:09:45PM -0500, Murali Karicheri wrote: > From: WingMan Kwok <w-kwok2@xxxxxx> > > The 10GBASE-R Physical Coding Sublayer (PCS-R) module provides > functionality of a physical coding sublayer (PCS) on data being > transferred between a demuxed XGMII and SerDes supporting a 16 > or 32 bit interface. From the driver point of view, whether > a ethernet link is up or not depends also on the status of the > block-lock bit of the PCSR. This patch adds the checking of that > bit in order to determine the link status. I would think this would be a common thing and the phy driver should provide the status, rather than trying to give the ethernet driver direct access to the phy registers. Is the PCSR the serdes phy or registers in addition to that? Rob -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
